H. B. Yoo, J. Yu, H. Kim, J. H. Ryu, S.-J. Choi, D. H. Kim, and D. M. Kim
"Deep Depletion Capacitance-Voltage Technique For Spatial Distribution of Traps Across the Substrate in MOS Structures"
Solid-State Electronics, vol. 173, p. 107905, 2020-10
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수정: 2023년 3월 27일
[4] "Deep Depletion Capacitance-Voltage Technique For Spatial Distribution of Traps Across the Substrate in MOS Structures"
[4] "Deep Depletion Capacitance-Voltage Technique For Spatial Distribution of Traps Across the Substrate in MOS Structures"
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